Production Data
WM8321
ADDRESS
R16440
BIT
LABEL
DEFAULT
DESCRIPTION
GPIOn pin direction
GPn_DIR
15
1
(4038h)
0 = Output
1 = Input
to
GPn_PULL
[1:0]
GPIOn Pull-Up / Pull-Down
configuration
14:13
01
R16451
(4043h)
00 = No pull resistor
01 = Pull-down enabled
10 = Pull-up enabled
11 = Reserved
GPn_INT_M
ODE
GPIOn Interrupt Mode
12
0
0 = GPIO interrupt is rising edge
triggered (if GPn_POL=1) or falling
edge triggered (if GPn_POL=0)
1 = GPIO interrupt is triggered on
rising and falling edges
GPn_PWR_D
OM
GPIOn Power Domain
See Table 56.
11
10
0
1
GPn_POL
GPIOn Polarity select
0 = Inverted (active low)
1 = Non-Inverted (active high)
GPIOn Output pin configuration
0 = CMOS
GPn_OD
9
7
0
0
1 = Open Drain
GPn_ENA
GPn_FN [3:0]
GPIOn Enable control
0 = GPIO pin is tri-stated
1 = Normal operation
GPIOn Pin Function
See Table 57.
3:0
0000
Note: n is a number between 1 and 12 that identifies the individual GPIO.
Note: The default values noted are valid when the WM8321 powers up to the OFF state, or if the
Register Map is reset following a Device Reset or Software Reset event. In the case of GPIO pins
1 to 6, these registers are overwritten with the respective ICE or OTP memory contents when an
ON transition is scheduled.
Table 54 GPIO Pin Configuration
When the GPIO output function is selected (GPn_FN = 0h, GPn_DIR = 0), the state of a GPIO output
is controlled by writing to the corresponding GPn_LVL register bit, as defined in Table 55.
The logic level of a GPIO input is determined by reading the corresponding GPn_LVL register bit. If
GPn_POL is set, then the read value of the GPn_LVL field for a GPIO input is the inverse of the
external signal. Note that, when the GPIO input level changes, the logic level of GPn_LVL will only be
updated after the maximum de-bounce period, as listed in Table 52. An input pulse that is shorter
than the minimum de-bounce period will be filtered by the de-bounce function and will be ignored.
If a GPIO is configured as a CMOS output (ie. GPn_OD = 0), then the read value of the GPn_LVL
field will indicate the logic level of that output. If GPn_POL is set, then the read value of the GPn_LVL
field for a GPIO output is the inverse of the level on the external pad.
If a GPIO is configured as an Open Drain output, then the read value of GPn_LVL is only valid when
the internal pull-up resistor is enabled on the pin (ie. when GPn_PULL = 10). The read value is also
affected by the GPn_POL bit, as described above for the CMOS case.
If a GPIO is tri-stated (GPn_ENA = 0), then the read value of the corresponding GPn_LVL field is
invalid.
PD, February 2012, Rev 4.0
111
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
