Production Data
WM8321
GPn_FN
GPIO INPUT
FUNCTION
DESCRIPTION
DE-BOUNCE
TIME
8h
Hardware DVS
control 1
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
None
Hardware DVS
control 2
Control input for selecting the DVS output
voltage in one or more DC-DC Converters.
See Section 15.6.
9h
Ah
Bh
Ch
None
Hardware
Enable 1
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
32s to 64s
32s to 64s
32s to 64s
Hardware
Enable 2
Control input for enabling one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Hardware
Control input 1
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Hardware
Control input 2
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Dh
Eh
Fh
32s to 64s
32ms to 64ms
32ms to 64ms
Hardware
Control input 1
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Hardware
Control input 2
Control input for selecting the operating mode
and/or output voltage of one or more DC-DC
Converters and LDO Regulators.
See Section 15.
Table 52 List of GPIO Input Functions
Further details of the GPIO input de-bounce time are noted in Section 21.3.
GPn_FN
GPIO OUTPUT
FUNCTION
DESCRIPTION
GPIO
GPIO output. Logic level is set by writing to the GPn_LVL
register bits. See Section 21.3.
0h
Oscillator clock
ON state
32.768kHz clock output. See Section 13.
1h
2h
Logic output indicating that the WM8321 is in the ON state. See
Section 11.5.
SLEEP state
Logic output indicating that the WM8321 is in the SLEEP state.
See Section 11.5.
3h
4h
Power State
Change
Logic output asserted whenever a Power On Reset, or an ON,
OFF, SLEEP or WAKE transition has completed.
Under default polarity (GPn_POL=1), the logic level is the same
as the PS_INT interrupt status flag. Note that, if any of the
associated Secondary interrupts is masked, then the respective
event will not affect the Power State Change GPIO output.
See Section 11.2 and Section 11.4.
DC-DC1 DVS
Done
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
8h
9h
DC-DC2 DVS
Done
Logic output indicating that DC-DC1 buck converter DVS slew
has been completed. This signal is temporarily de-asserted
during voltage transitions (including non-DVS transitions). See
Section 15.6.
PD, February 2012, Rev 4.0
109
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
