WM8321
Production Data
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4 = Reserved
5 = Chip Temperature
6 = Reserved
7 = PVDD voltage
DCMP4_GT
Digital Comparator 4 interrupt control
12
0
0 = interrupt when less than
threshold
1 = interrupt when greater than or
equal to threshold
DCMP4_THR
Digital Comparator 4 threshold
11:0
000h
(12-bit unsigned binary number;
coding is the same as AUX_DATA)
Table 47 AUXADC Digital Comparator Control
18.5 AUXADC INTERRUPTS
The AUXADC is associated with a number of Interrupt event flags to indicate when new AUXADC
data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed.
Each of these secondary interrupts triggers a primary AUXADC Interrupt, AUXADC_INT (see
Section 23). This can be masked by setting the mask bit(s) as described in Table 48.
Note that AUXADC_DATA_EINT is not cleared by reading the measured AUXADC data, it can only
be cleared by writing ‘1’ to the AUXADC_DATA_EINT register.
The AUXADC interrupts can be programmed using bits in Table 48.
ADDRESS
R16401
(4011h)
BIT
LABEL
DESCRIPTION
AUXADC Data Ready interrupt
(Rising Edge triggered)
AUXADC_DATA_EINT
8
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
AUXADC Digital Comparator n interrupt
(Trigger is controlled by DCMPn_GT)
Note: Cleared when a ‘1’ is written.
Interrupt mask.
AUXADC_DCOMPn_EINT
7:4
8
R16409
(4019h)
IM_AUXADC_DATA_EINT
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Interrupt mask.
IM_AUXADC_DCOMPn_EI
7:4
NT
0 = Do not mask interrupt.
1 = Mask interrupt.
Default value is 1 (masked)
Note: n is a number between 1 and 4 that identifies the individual Comparator.
Table 48 AUXADC Interrupts
PD, February 2012, Rev 4.0
102
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
