WM8216
Production Data
SERIAL INTERFACE
Figure 3 Serial Interface Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SCK period
tSPER
83.3
ns
SCK high
tSCKH
tSCKL
tSSU
37.5
37.5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK low
SDI set-up time
SDI hold time
tSH
6
SCK to SEN set-up time
SEN to SCK set-up time
SEN pulse width
tSCE
12
12
60
tSEC
tSEW
tSERD
tSCRD
tSCRDZ
SEN low to SDO = Register data
SCK low to SDO = Register data
SCK low to SDO = ADC data
30
30
30
Note: 1.
Parameters are measured at 50% of the rising/falling edge
INTERNAL POWER ON RESET CIRCUIT
Figure 4 Internal Power On Reset Circuit Schematic
The WM8216 includes an internal Power-On-Reset Circuit, as shown in Figure 4, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.
PD Rev 4.0 March 2007
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
