WM8196
Production Data
INTERNAL POWER ON RESET CIRCUIT
Figure 6 Internal Power On Reset Circuit Schematic
The WM8196 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.
The power supplies can be brought up in any order but is important that either AVDD is brought up
and is stable before DVDD comes up or vice versa as shown in Figure 7 and Figure 8.
Figure 7 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 7 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. Now AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released
high and all registers are in their default state and writes to the control interface may take place.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold Vpora_off.
PD Rev 4.3 March 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
