WM8196
Production Data
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
tVSMPH
tVSMPSU
VSMP
INPUT
tVSU
tVH
tRSU
tRH
VIDEO
Figure 1 Input Video Timing
Note:
1.
See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
tPER
41.6
ns
MCLK high period
MCLK low period
VSMP set-up time
VSMP hold time
tMCLKH
tMCLKL
tVSMPSU
tVSMPH
tVSU
18.8
18.8
6
ns
ns
ns
ns
ns
ns
ns
ns
3
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
Notes:
10
3
tVH
tRSU
10
3
tRH
1.
2.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
tPD
OP[7:0]
Figure 2 Output Data Timing
PD Rev 4.3 March 2007
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
