WM8196
Production Data
PIN DESCRIPTION
PIN
1
NAME
RINP
TYPE
Analogue input
Supply
DESCRIPTION
Red channel input video.
Analogue ground (0V).
2
AGND2
DVDD1
3
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
4
5
6
OEB
VSMP
Digital input
Digital input
Digital input
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC/ACYC
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if
used on every pixel. ACYC autocycles between R, G, B inputs.
7
MCLK
Digital input
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
8
DGND
SEN
Supply
Digital ground (0V).
9
Digital input
Supply
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Serial data input.
10
11
12
DVDD2
SDI
Digital input
Digital input
SCK
Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in two multiplexed formats as shown, under
the control of register MUXOP [1:0]
See ‘Output Formats’ description in Device Description section for further details.
8+8-bit
4+4+4+4-bit
A
B
A
B
C
D
13
14
15
16
17
18
19
20
OP[0]
OP[1]
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d8
d0
d1
d2
d3
d4
d5
d6
d7
d9
OP[2]
d10
d11
d12
d13
d14
d15
OP[3]
OP[4]
d12
d13
d14
d15
d8
d9
d4
d5
d6
d7
d0
OP[5]
d1
d2
d3
OP[6]
d10
d11
OP[7]/SDO
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device
Description section for further details.
21
22
23
AVDD
AGND1
VRB
Supply
Supply
Analogue supply (5V). This must be operated at the same potential as DVDD1.
Analogue ground (0V).
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
24
25
26
VRT
VRX
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
27
28
BINP
GINP
Analogue input
Analogue input
Blue channel input video.
Green channel input video.
PD Rev 4.3 March 2007
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
