WM8195
Production Data
PIN DESCRIPTION
PIN
NAME
TYPE
Analogue output Input return bias voltage.
This pin must be decoupled to AGND via a capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
DESCRIPTION
1
VRX
2
VRLC/VBIAS
Analogue I/O
This pin would typically be decoupled to AGND via a capacitor.
VRLC can be externally driven if programmed Hi-Z.
3
4
AGND1
BINP
Supply
Analogue input
Supply
Analogue ground (0V).
Blue channel input video.
Analogue ground (0V).
Green channel input video.
Analogue ground (0V).
Red channel input video.
Analogue ground (0V).
5
AGND2
GINP
6
Analogue input
Supply
7
AGND3
RINP
8
Analogue input
Supply
9
AGND4
DVDD1
10
Supply
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
11
12
OEB
Digital input
Digital input
Output Hi-Z control, all digital outputs disabled when OEB = 1.
SEN/STB
Serial interface: enable pulse, active high
Parallel interface: strobe, active low
Latched on NRESET rising edge: if Low then device control is via serial interface,
if high then device control is via parallel interface.
13
14
SDI/DNA
Digital input
Digital input
Serial interface: serial input data signal
Parallel interface:
High = data, Low = address
SCK/RNW
Serial interface: serial clock signal
Parallel interface:
High: OP[13:6] is output bus.
Low: OP[13:6] is input bus (Hi-Z).
15
16
VSMP
Digital input
Digital input
Video sample synchronisation pulse.
RLC/ACYC
RLC (active high) selects reset level
clamp on a pixel-by-pixel basis – tie high
if used on every pixel.
ACYC autocycles between R, G, B
inputs when in Line-by-Line mode.
17
MCLK
Digital input
Supply
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
18
19
20
21
22
23
DGND1
NC
Digital ground (0V).
No connection.
NC
No connection.
OP[0]
OP[1]
OP[2]
Digital output
Digital output
Digital output
Pins OP[13:0] form a Hi-Z digital bi-directional bus. There are several modes:
Hi-Z: when OEB = 1.
14-bit output: 14-bit data is output on OP[13:0].
8-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate.
7-bit multiplexed output: data is output on OP[13:6] at 2 ADC conversion rate.
4-bit multiplexed output: data is output on OP[13:10] at 4 ADC conversion rate.
See Output Formats section in Device Description for further details.
Input 8-bit: control data is input on OP[13:6] in parallel mode when SCK/RNW = 0,
and SEN/STB = 0.
Output 8-bit: register read back data is output in parallel on OP[13:6] when
SCK/RNW = 1, and SEN/STB = 0, or in serial on pin SDO when SEN/STB = 1.
24
25
26
27
28
29
30
DVDD2
DGND2
OP[3]
Supply
Supply
Digital I/O supply (3.3V/5V).
Digital ground (0V).
Digital output
Digital output
Digital output
Digital I/O
Supply
See pins 21 to 23 for details.
OP[4]
OP[5]
OP[6]
DGND3
Digital ground (0V).
PD Rev 4.1 July 2005
4
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
