Production Data
WM8195
DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8195. The register map is programmed by writing the required codes to the appropriate
addresses via the serial or parallel interface.
ADDRESS
<a5:a0>
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
100000
100001
DESCRIPTION
DEF
(hex)
03
RW
BIT
b7
b6
b5
b4
PGAFS[0]
0
b3
b2
b1
b0
Setup Reg 1
Setup Reg 2
Setup Reg 3
Software Reset
Auto-cycle Reset
Setup Reg 4
Revision Number
Setup Reg 5
Setup Reg 6
Reserved
RW
RW
RW
W
MODE4
DEL[0]
PGAFS[1]
RLCDACRNG
CDSREF [1]
SELPD
MONO
INVOP
RLCV[2]
CDS
EN
20
DEL[1]
VRLCEXT
RLCV[3]
MUXOP[1]
RLCV[1]
MUXOP[0]
RLCV[0]
1F
00
CHAN[1] CHAN[0]
CDSREF [0]
00
W
00
RW
R
FM[1]
FM[0]
INTM[1]
INTM[0]
RLCINT
FME
ACYCNRLC
LINEBYLINE
41
00
RW
RW
RW
RW
RW
RW
RW
0
0
0
POSNNEG
VDEL[2]
VDEL[1]
VDEL[0]
VSMPDET
00
0
0
0
0
SELDIS[3]
SELDIS[2]
SELDIS[1]
SELDIS[0]
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
00
Reserved
00
0
0
0
0
0
0
0
0
DAC Value (Red)
80
DAC[7]
DAC[7]
DAC[6]
DAC[6]
DAC[5]
DAC[5]
DAC[4]
DAC[4]
DAC[3]
DAC[3]
DAC[2]
DAC[2]
DAC[1]
DAC[1]
DAC[0]
DAC[0]
DAC Value
(Green)
80
100010
100011
101000
101001
DAC Value (Blue)
DAC Value (RGB)
PGA Gain (Red)
80
80
00
00
RW
W
DAC[7]
DAC[7]
PGA[7]
PGA[7]
DAC[6]
DAC[6]
PGA[6]
PGA[6]
DAC[5]
DAC[5]
PGA[5]
PGA[5]
DAC[4]
DAC[4]
PGA[4]
PGA[4]
DAC[3]
DAC[3]
PGA[3]
PGA[3]
DAC[2]
DAC[2]
PGA[2]
PGA[2]
DAC[1]
DAC[1]
PGA[1]
PGA[1]
DAC[0]
DAC[0]
PGA[0]
PGA[0]
RW
RW
PGA Gain
(Green)
101010
101011
PGA Gain (Blue)
PGA Gain (RGB)
00
00
RW
W
PGA[7]
PGA[7]
PGA[6]
PGA[6]
PGA[5]
PGA[5]
PGA[4]
PGA[4]
PGA[3]
PGA[3]
PGA[2]
PGA[2]
PGA[1]
PGA[1]
PGA[0]
PGA[0]
Table 6 Register Map
PD Rev 4.1 July 2005
27
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
