WM8181
Advanced Information
During the reset period of the video waveform the user applies a logic high signal to the CLAMP pin,
connecting the VINP pin to the VINM pin. This is illustrated in Figure 10. This has the effect of
charging, or discharging, the VINM side of the coupling capacitor to the black reference voltage
applied to VINP. When the CLAMP pin is taken low again the voltage across the capacitor will stay at
a fixed value and the input to the WM8181 will follow the output from the CCD. The WM8181
therefore converts the true value of the video signal, VRS – VVS
.
VRS
VIDEO
SIG NAL
VVS
CLAM P
OPEN
CLO SED
OPEN
CLO SED
OPEN
CLO SED
SW ITCH
CLAM P
Figure 10 Clamp Switch Operation.
ADJUSTING THE ADC INPUT RANGE
The WM8181 normally uses an internal bandgap reference to generate the ADC reference voltages.
With the recommended decoupling on the VRT and VRB pins, this ensures that the ADC receives
the cleanest reference voltages and thus achieves the optimum performance. The full scale input
range of the ADC is fixed in this mode to be 1.5V and is largely independent of supply voltage
variations. VREFIN should be connected to AVDD in this case.
It is possible to adjust the input range of the ADC by applying an externally generated voltage to the
VREFIN pin. The value of the ADC references and the corresponding input range of the ADC can be
determined from Table 1 in the Device Description section of this datasheet. Care must be taken to
avoid any noise on the VREFIN pin, as any noise on this pin with respect to AGND will degrade the
performance of the WM8181.
AI Rev 3.0 January 2000
12
WOLFSON MICROELECTRONICS LTD
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
