WM8152
Production Data
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
tVSMPH
tVSMPSU
VSMP
INPUT
tVSU
tVH
tRSU
tRH
VIDEO
Figure 1 Input Video Timing
Note:
1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
tPER
41.6
ns
MCLK high period
MCLK low period
tMCLKH
tMCLKL
tVSMPSU
tVSMPH
tVSU
18.8
18.8
6
ns
ns
ns
ns
ns
ns
ns
ns
VSMP set-up time
VSMP hold time
3
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
10
3
tVH
tRSU
10
3
tRH
Notes:
1.
2.
t
VSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
tPD
tPD
OP[3:0]
Figure 2 Output Data Timing
Test Conditions
VDD = 5.0V, DVDD = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
OH = 1mA, IOL = 1mA
MIN
TYP
MAX
UNITS
Output propagation delay
tPD
I
20
ns
PD Rev 4.0 January 2004
8
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
