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WM8152CDS 参数 Datasheet PDF下载

WM8152CDS图片预览
型号: WM8152CDS
PDF下载: 下载PDF文件 查看货源
内容描述: 单通道16位CIS / CCD AFE与4位宽输出 [Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output]
分类和应用: 光电二极管
文件页数/大小: 26 页 / 284 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8152  
Production Data  
ELECTRICAL CHARACTERISTICS  
Test Conditions  
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST  
MIN  
TYP  
MAX  
UNIT  
CONDITIONS  
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)  
Full-scale input voltage range  
(see Note 1)  
Max Gain  
Min Gain  
0.30  
3.22  
Vp-p  
Vp-p  
V
Input signal limits (see Note 2)  
Full-scale transition error  
VIN  
0
VDD  
+50  
Gain = 0dB;  
PGA[7:0] = 07(hex)  
-50  
10  
10  
mV  
Zero-scale transition error  
Gain = 0dB;  
-50  
+50  
mV  
PGA[7:0] = 07(hex)  
Differential non-linearity  
Integral non-linearity  
Total output noise  
DNL  
INL  
1.25  
25  
LSB  
LSB  
Min Gain  
Max Gain  
4.5  
14  
LSB rms  
LSB rms  
References  
Upper reference voltage  
VRT  
VRB  
VRX  
VRTB  
2.70  
1.45  
1.65  
1.25  
1
V
V
V
V
Lower reference voltage  
Input return bias voltage  
1.55  
1.15  
1.75  
1.35  
Diff. reference voltage (VRT-VRB)  
Output resistance VRT, VRB, VRX  
VRLC/Reset-Level Clamp (RLC)  
RLC switching impedance  
VRLC short-circuit current  
VRLC output resistance  
20  
50  
2
100  
4.5  
mA  
1.86  
2
VRLC Hi-Z leakage current  
RLCDAC resolution  
VRLC = 0 to AVDD  
AVDD = 5.0V  
1
µA  
4
bits  
V/step  
V/step  
V
RLCDAC step size, RLCDAC = 0  
RLCDAC step size, RLCDAC = 1  
VRLCSTEP  
VRLCSTEP  
VRLCBOT  
0.23  
0.14  
0.34  
0.25  
0.16  
0.39  
0.27  
0.20  
0.44  
RLCDAC output voltage at  
AVDD = 5.0V  
code 0(hex), RLCDACRNG = 0  
RLCDAC output voltage at  
code 0(hex), RLCDACRNG = 1  
VRLCBOT  
VRLCTOP  
VRLCTOP  
0.20  
4.0  
0.26  
4.16  
2.66  
0.31  
4.3  
V
V
V
RLCDAC output voltage at  
code F(hex) RLCDACRNG, = 0  
AVDD = 5.0V  
RLCDAC output voltage at  
2.56  
2.76  
code F(hex), RLCDACRNG = 1  
Offset DAC, Monotonicity Guaranteed  
Resolution  
8
bits  
LSB  
Differential non-linearity  
Integral non-linearity  
Step size  
DNL  
INL  
0.1  
0.5  
1
0.25  
2.04  
-260  
+260  
LSB  
mV/step  
mV  
Output voltage  
Code 00(hex)  
Code FF(hex)  
-247  
-273  
+247  
+273  
mV  
Notes:  
1.  
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input  
range.  
2.  
Input signal limits are the limits within which the full-scale input voltage signal must lie.  
PD Rev 4.0 January 2004  
6
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