WM2637
Production Data
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
code
Output voltage = 2
1111
(
VREF
)
1024
OUTPUT
INPUT
11
1111
1023
1024
2
(
VREF
)
:
:
513
1024
10
10
0000
0001
0000
(
)
REF
2V
0000
1111
512
2
(
VREF
)
= VREF
1024
01
1111
511
2
2
(
(
VREF
)
1024
:
:
00
0000
0001
0000
1
VREF
)
1024
0000
0000
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2kW load with a 100pF load capacitance.
SERIAL INTERFACE
When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data
clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the input
register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then transfers
the data to the DAC latch. When NCS is high, input data cannot be clocked into the input register
(see Table 2).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC
settling time to 10 bits limits the update rate for large input step transitions.
SOFTWARE CONFIGURATION OPTIONS
The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the 10-bit data
word. D15-D12 hold the programmable options which are summarized Table 3
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
x
D0
x
R1 SPD PWD R0
New DAC value or control register value
Table 2 Serial Word Format
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
7