WM2637
Production Data
SERIAL INTERFACE
tSUCSS
tDCS1
NCS
SCLK
DIN
tSUCS1
tSUCS2
tWCL
tWCH
tSUDCLK
tHDCLK
D15
D14
D13
D12
D11
D0
Figure 1 Timing Diagram
Test Conditions:
RL = 10kW, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating free-
air temperature range (unless noted otherwise)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time NCS low before SCLK low
tSUCSS
10
ns
Setup time, rising edge of SCLK to rising edge of NCS,
external end of write
tSUCS1
tSUCS2
10
ns
Setup time, rising edge of SCLK to falling edge of NCS,
start of next write cycle
5
ns
ns
ns
ns
ns
Pulse duration, SCLK high
tWCL
tWCH
tSUDCLK
tHDCLK
25
25
10
5
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
