欢迎访问ic37.com |
会员登录 免费注册
发布采购

WM2626 参数 Datasheet PDF下载

WM2626图片预览
型号: WM2626
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗双8位串行输入DAC ,内置电压基准 [Low Power Dual 8-bit Serial Input DAC with Internal Reference]
分类和应用:
文件页数/大小: 11 页 / 111 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
 浏览型号WM2626的Datasheet PDF文件第3页浏览型号WM2626的Datasheet PDF文件第4页浏览型号WM2626的Datasheet PDF文件第5页浏览型号WM2626的Datasheet PDF文件第6页浏览型号WM2626的Datasheet PDF文件第7页浏览型号WM2626的Datasheet PDF文件第9页浏览型号WM2626的Datasheet PDF文件第10页浏览型号WM2626的Datasheet PDF文件第11页  
WM2626  
Production Data  
SOFTWARE CONFIGURATION OPTIONS  
Table 2 shows the composition of a 16-bit data word. D11-D4 contains the 8-bit data word, and  
D14-D13 hold the programmable options. Bits D15 and D12 are used for addressing the different  
latches. D3 to D0 are unused and should be set to ZERO.  
D15 D14 D13 D12 D11 D10 D9  
D8  
D7 D6 D5  
D4  
D3  
0
D2 D1 D0  
R1 SPD PWR R0  
New DAC value (8 bits)  
0
0
0
Table 2 Register Map  
PROGRAMMABLE CONVERTER SPEED  
SPD (Bit 14) allows for software control of the converter speed. A ONE selects the fast mode,  
where typical settling time to within ±0.5LSB of the final value is 0.8µs. a ZERO puts the device into  
the slow mode, where typical settling time is 2.8µs.  
PROGRAMMABLE POWER DOWN  
The power down function is controlled by PWR (Bit 13). A ZERO configures the device as active,  
or fully powered up, a ONE configures the device into power down mode. When the power down  
function is released the device reverts to the DAC code set prior to power down.  
REGISTER ADDRESSING  
Data received on the serial interface is routed according to the values of bits R1 and R0, as shown  
in Table 3.  
R1  
R0  
(BIT D15)  
(BIT D12)  
REGISTER  
0
0
1
1
0
1
0
1
Write data to DAC B and buffer  
Write data to buffer  
Write data to DAC A and update DAC B with buffer content  
Write data to control register  
Table 3 Latch Addressing  
To update both DACs simultaneously, the data intended for DAC B should first be stored in the  
buffer. Subsequently, writing data to DAC A will automatically update the DAC B latch from the  
buffer, so that the analogue output of both DACs will change at the same time.  
When updating the two channels independently, all data written to the DAC B latch (R1 and R0 set  
to ZERO) is also copied to the buffer. Thus the automatic update of DAC B when writing to DAC A  
latch (R1=1, R0=0) does not change the DAC B data. Data should not be written only to the buffer  
when operating in this mode.  
The contents of the control register, shown below in Table 4, are used to program the internal  
reference function.  
D11 D10 D9  
D8  
x
D7  
x
D6  
x
D5  
x
D4  
x
D3  
x
D2  
x
D1  
D0  
x
x
x
REF1 REF0  
Table 4 Control Register Contents  
PROGRAMMABLE INTERNAL OR EXTERNAL REFERENCE  
The reference can be sourced internally or externally under software control, as detailed in Table 5.  
If an external reference voltage is applied to the REF pin, the device must be configured to accept  
this. This will activate the reference input buffer, whose input resistance of 10M(typical) makes  
the reference input resistance independent of code.  
REF1  
REF0  
FUNCTION  
Use external reference  
0
0
1
1
0
1
0
1
Use internal 1.024V reference  
Use internal 2.048V reference  
Use external reference  
Table 5 Programmable Internal Reference  
When using the on-chip reference, voltages of 1.024V or 2.048V are available. The internal  
reference can source up to 1mA on the REF pin and can therefore be used as a system reference  
for external components.  
WOLFSON MICROELECTRONICS LTD  
PD Rev 1.0 April 2001  
8