WM2626
Production Data
Test Conditions:
RL = 10kΩ, CL = 100pF. VDD = 5V ±10%, VREF = 2.048V and VDD = 3V ±10%, VREF = 1.024V over recommended operating free-
air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference Output (Internal reference)
Low reference voltage
VREFL
VREFH
IREF
1.003
2.027
1.024
2.048
1.045
2.069
±1
V
V
High reference voltage
Output Current
mA
pF
Load capacitance
100
Reference Input (External reference)
Reference input resistance
Reference input capacitance
Reference feedthrough
RREFIN
CREFIN
10
5
MΩ
pF
V
REF = 1VPP at 1kHz
-80
dB
+ 1.024V dc, DAC code 0
Reference input bandwidth
V
REF = 0.2VPP + 1.024V dc
DAC code 128
Slow
0.525
1.3
MHz
MHz
Fast
Digital Inputs
High level input current
Low level input current
Input capacitance
Notes:
IIH
IIL
CI
Input voltage = VDD
Input voltage = 0V
1
µA
µA
pF
-1
8
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage always changes in the same direction (or remains constant) as
the digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is
expressed as a percentage of the full scale output voltage with a 10kΩ load.
8. IDD is measured while continuously writing code 128 to the DAC. For VIH < VDD - 0.7V and VIL > 0.7V supply current will
increase.
9. Slew rate is for an output change from 10% to 90% of full-scale output voltage, or vice versa. The results are for the lower
value of the rising and falling edge slew rates.
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
11. SNR, SNRD, THD and SPFDR are measured on a synthesised sine wave at frequency fOUT generated with a sampling
frequency fs.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
4
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
