Production Data
WM2626
SERIAL INTERFACE
tWL
tWH
3
tSUC16CS
1
2
4
5
15
16
SCLK
tSUD
D15
tSUCSCK
tHD
D14
D13
D12
D1
D0
DIN
NCS
Figure 1 Timing Diagram
Test Conditions:
RL = 10kΩ, CL = 100pF. VDD = 5V ± 10%, VREF = 2.048V and VDD = 3V ± 10%, VREF = 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time, NCS low before first falling SCLK edge
tSUCSCK
10
ns
Setup time, 16th falling SCLK edge (when data bit D0
is sampled) before NCS rising edge.
tSUC16CS
10
ns
Pulse duration, SCLK high.
tWH
tWL
tSUD
tHD
25
25
10
5
ns
ns
ns
ns
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
