WM2613
Production Data Rev 1.0
SERIAL INTERFACE
tSUD
tHD
X
Data
X
D[0-7]
A[0-1]
NCS
tSUA
tHA
X
Address
X
tSUCSWE
tWWE
NWE
tSUWELD
tWLD
NLDAC
Figure 1 Timing Diagram
SYMBOL
TEST CONDITIONS
MIN
TYP
13
MAX
UNIT
ns
tSUCSWE
tSUDWE
tHD
Setup time NCS low before positive NWE edge
Data ready before positive NWE edge
Data hold after positive NWE edge
Setup time for address bits A0, A1
Address hold after positive NWE edge
Positive NWE edge before NLDAC low
High pulse width of NWE
9
0
ns
ns
tSUA
17
0
ns
tHA
tSUWELD
tWWE
tWLD
0
ns
ns
ns
10
10
Low pulse width of NLDAC
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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