W90P710CD/W90P710CDG
Ethernet MAC Controller
y
y
y
y
y
y
y
y
y
y
y
y
DMA engine with burst mode
MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
Data alignment logic
Endian translation
100/10-Mbit per second operation
Full compliance with IEEE standard 802.3
RMII interface only
Station Management Signaling
On-Chip CAM (up to 16 destination addresses)
Full-duplex mode with PAUSE feature
Long/short packet modes
PAD generation
LCD Controller (LCDC)
(1)
STN LCD Display
y
Supports 4-bit single scan Monochrome STN LCD panel, 8-bit single scan Monochrome STN LCD
panel, 8-bit single scan Color STN LCD panel
y
y
y
y
Up to 16 gray levels display for Monochrome STN LCD panel
Up to 4096(12bpp) colors display for Color STN LCD panel
Virtual coloring method: Frame Rate Control (16-level)
Anti-flickering method: Time-based Dithering
(2)
y
TFT LCD Display
Supports Sync-type TFT LCD panel and Sync-type High-color TFT LCD panel
Supports direct or palettized color display
y
(3)
TV Encoder
y
Supports 8-bit YCbCr data output format to connect with external TV Encoder
(4)
y
LCD Preprocessing
Supports RGB Raw-data or packetd YUV422 format
Programmable parameters for different image size
y
y
Build in two FIFOs, FIFO 1 is for Video image and FIFO 2 is for OSD image. Each FIFO is 16
words deep
Publication Release Date: September 19, 2006
- 7 -
Revision B2
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