W90P710CD/W90P710CDG
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 6
FEATURES................................................................................................................................. 6
PIN DIAGRAM .......................................................................................................................... 13
PIN ASSIGNMENT ................................................................................................................... 14
PIN DESCRIPTION................................................................................................................... 20
FUNCTIONAL DESCRIPTION ................................................................................................. 33
6.1
6.2
ARM7TDMI CPU CORE............................................................................................... 33
System Manager........................................................................................................... 34
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
Overview ......................................................................................................................34
System Memory Map....................................................................................................34
Address Bus Generation ..............................................................................................37
Data Bus Connection with External Memory ................................................................37
Bus Arbitration..............................................................................................................46
Power management .....................................................................................................47
Power-On Setting .........................................................................................................49
System Manager Control Registers Map......................................................................50
6.3
6.4
External Bus Interface .................................................................................................. 64
6.3.1
6.3.2
6.3.3
EBI Overview................................................................................................................64
SDRAM Controller........................................................................................................64
EBI Control Registers Map...........................................................................................68
Cache Controller........................................................................................................... 86
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
On-Chip RAM...............................................................................................................86
Non-Cacheable Area....................................................................................................86
Instruction Cache..........................................................................................................87
Data Cache ..................................................................................................................89
Write Buffer ..................................................................................................................91
Cache Control Registers Map.......................................................................................91
6.5
6.6
6.7
Ethernet MAC Controller............................................................................................... 97
6.5.1
6.5.2
EMC Functional Description.........................................................................................98
EMC Register Mapping ..............................................................................................108
GDMA Controller ........................................................................................................ 161
6.6.1
6.6.2
GDMA Functional Description ....................................................................................161
GDMA Register Map ..................................................................................................162
USB Host Controller ................................................................................................... 171
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
USB Host Functional Description ...............................................................................171
USB Host Controller Registers Map ...........................................................................172
HCCA .........................................................................................................................194
Endpoint Descriptor....................................................................................................194
Transfer Descriptor.....................................................................................................194
6.8
USB Device Controller................................................................................................ 194
Publication Release Date: September 19, 2006
- 3 -
Revision B2
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