W90P710CD/W90P710CDG
y
When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
Smart Card Host Interface (SCHI)
y
y
y
y
y
y
y
y
ISO-7816 compliant
PC/SC T=0, T=1 compliant
16-byte transmitter FIFO and 16-byte receiver FIFO
FIFO threshold interrupt to optimize system performance
Programmable transmission clock frequency
Versatile baud rate configuration
UART-like register file structure
General-purpose C4, C8 channels
SD Host Interface
y
Directly connect to Secure Digital (SD, MMC) flash memory card.
y
Supports DMA function to accelerate the data transfer between the internal buffer, external
SDRAM, and flash memory card.
y
y
Two 512 bytes internal buffers are embedded inside the controller.
No SPI mode.
KeyPad Scan Interface
y
Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4 rows by 8 columns array
without auxiliary component
y
y
y
Programmable debounce time
One or two keys scan with interrupt and three keys reset function.
Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
y
y
y
APB slave consisted of PS2 protocol.
Connect IBM keyboard or bar-code reader through PS2 interface.
Provide hardware scan code to ASCII translation
Power management
y
y
y
y
y
Programmable clock enables for individual peripheral
IDLE mode to halt ARM Core and keep peripheral working
Power-Down mode to stop all clocks included external crystal oscillator.
Exit IDLE by all interrupts
Exit Power-Down by keypad,USB device and external interrupts
Publication Release Date: September 19, 2006
Revision B2
- 11 -
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