W90P710CD/W90P710CDG
3. PIN DIAGRAM
USB1VDD
DP1
nWAIT/TREQB
nOE
nECS[0]
nECS[1]
nECS[2]
VDD33
VSS33
nECS[3]
D[24]/VD[16]/GPIO[60]
D[25]/VD[17]/GPIO[61]
D[26]/VD[18]/GPIO[62]
DN1
130
125
120
USB1VSS
USB0VSS
DN0
DP0
USB0VDD
VDD33
5
TXD0/GPIO[5]
RXD0/GPIO[6]
TXD1/GPIO[7]
RXD1/GPIO[8]
10
15
20
25
30
35
40
D[27]/VD[19]/GPIO[63]
VDD33
CTS1/TXD2(IrDA)/PS2_CLK/GPIO[9]
RTS1/RXD2(IrDA)/PS2_DATA/GPIO[10]
VSS33
D[28]/VD[20]/GPIO[64]
D[29]/VD[21]/GPIO[65]
D[30]/VD[22]/GPIO[66]
SCL0/SFRM/TIMER0/GPIO[11]
SDA0/SSPTXD/TIMER1/GPIO[12]
SCL1/SCLK/KPI_ROW[3]/GPIO[13]
D[31]/VD[23]/GPIO[67]
A[21]
115
110
105
VSS33
A[20]
A[19]
A[18]
A[17]/TREQA
VDD18
A[16]/TACK
A[15]/TBUS[31]
A[14]/TBUS[30]
VSS18
A[13]/TBUS[29]
A[12]/TBUS[28]
A[11]/TBUS[27]
SDA1/SSPRXD/KPI_ROW[2]/GPIO[14]
VDD18
VSS18
W90P710
KPI_ROW[0]/VCLK/GPIO[30]
KPI_ROW[1]/VDEN/GPIO[31]
KPI_ROW[2]/VSYNC/GPIO[32]
KPI_ROW[3]/HSYNC/GPIO[33]
KPI_COL[7]/VD[7]/GPIO[41]
KPI_COL[6]/VD[6]/GPIO[40]
KPI_COL[5]/VD[5]/GPIO[39]
KPI_COL[4]/VD[4]/GPIO[38]
KPI_COL[3]/VD[3]/GPIO[37]
KPI_COL[2]/VD[2]/GPIO[36]
KPI_COL[1]/VD[1]/GPIO[35]
176 -pin
LQFP
A[10]/TBUS[26]
VDD33
100
95
KPI_COL[0]/VD[0]/GPIO[34]
A[9]/TBUS[25]
A[8]/TBUS[24]
A[7]/TBUS[23]
A[6]/TBUS[22]
A[5]/TBUS[21]
VSS33
A[4]/TBUS[20]
A[3]/TBUS[19]
A[2]/TBUS[18]
A[1]/TBUS[17]
A[0]/TBUS[16]
VDD33
VSS33
nRESET
TEST
PLL0VDD18
PLL0VSS18
PLL1VSS18
PLL1VDD18
nIRQ[0]/GPIO[16]
nIRQ[1]/GPIO[17]
90
Fig 3.1 Pin Diagram
Publication Release Date: September 19, 2006
Revision B2
- 13 -
WINBOND [ WINBOND ]
