W90N745CD/W90N745CDG
PWM Clock Select Register (PWM_CSR)
REGISTER
PWM_CSR
ADDRESS
R/W
DESCRIPTION
RESET VALUE
0xFFF8_7004 R/W PWM Clock Select Register
0x0000_0000
31
23
15
30
22
14
6
29
21
13
28
20
12
4
27
19
11
26
18
10
2
25
17
9
24
16
8
Reserved
Reserved
Reserved
7
CSR3
5
Reserved
3
CSR2
1
0
Reserved
CSR1
Reserved
CSR0
BITS
[14:12]
[10:8]
[6:4]
DESCRIPTIONS
CSR3
CSR2
CSR1
CSR0
Select clock input for channel 3
Select clock input for channel 2.
Select clock input for channel 1
Select clock input for channel 0
[2:0]
CSR3
INPUT CLOCK DIVIDED BY
000
001
010
011
100
2
4
8
16
1
Publication Release Date: September 22, 2006
Revision A2
- 363 -
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