W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[2]
[1]
[0]
EPB_RDY
EPB_RST
EPB_EN
The memory is ready for Endpoint B to access
Endpoint B reset
Endpoint B enable
USB Endpoint B interrupt enable Register (EPB_IE)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EPB_IE
0xFFF0606C
R/W
USB endpoint B Interrupt Enable register 0x0000_0000
31
23
30
29
21
28
20
27
Reserved
19
Reserved
11
Reserved
26
18
25
17
24
16
22
14
6
15
13
12
10
9
8
7
5
4
3
2
1
0
EPB_BUS_ERR_IE
EPB_CF_IE
EPB_DMA_IE
EPB_ALT_IE
EPB_TK_IE EPB_STL_IE
Reserved
BITS
[31:6]
[5]
DESCRIPTIONS
Reserved
EPB_CF_IE
Endpoint B clear feature interrupt enable
[4]
EPB_BUS_ERR_IE
EPB_DMA_IE
EPB_ALT_IE
EPB_TK_IE
Endpoint B system bus error interrupt enable
Endpoint B DMA transfer complete interrupt enable
Endpoint B alternate setting interrupt enable
Endpoint B token input interrupt enable
Endpoint B stall interrupt enable
[3]
[2]
[1]
[0]
EPB_STL_IE
Publication Release Date: September 22, 2006
Revision A2
- 217 -
WINBOND [ WINBOND ]
