W90N745CD/W90N745CDG
Continued.
BITS
DESCRIPTIONS
[15:12]
[11:8]
[7:4]
EPB_ALT
EPB_INF
EPB_CFG
EPB_NUM
Endpoint B alternative setting (READ ONLY)
Endpoint B interface
Endpoint B configuration
Endpoint B number
[3:0]
USB Endpoint B Control Register (EPB_CTL)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EPB_CTL
0xFFF06068
R/W
USB endpoint B control register
0x0000_0000
31
23
30
29
21
28
27
19
26
18
25
24
16
Reserved
20
22
14
17
9
Reserved
15
13
12
11
10
8
Reserved
4
7
6
5
3
2
1
0
Reserved
EPB_ZERO
EPB_STL_CLR
EPB_THRE
EPB_STL
EPB_RDY
EPB_RST
EPB_EN
BITS
DESCRIPTIONS
Reserved
[31:7]
[6]
[5]
EPB_ZERO
Send zero length packet back to HOST
Clear the Endpoint B stall(WRITE ONLY)
Endpoint B threshold (only for ISO)
EPB_STL_CLR
EPB_THRE
EPB_STL
1: once available space in FIFO over 16 bytes, DMA
accesses memory
[4]
[3]
0: once available space in FIFO over 32 bytes, DMA
accesses memory
Set the Endpoint B stall
- 216 -
WINBOND [ WINBOND ]
