W90N745CD/W90N745CDG
BITS
[31:6]
[6]
DESCRIPTIONS
Reserved
EPA_ZERO
Send zero length packet to HOST
[5]
EPA_STL_CLR
CLEAR the Endpoint A stall(WRITE ONLY)
Endpoint A threshold (only for ISO)
1: once available space in FIFO over 16 bytes, DMA accesses
memory
[4]
EPA_THRE
0: once available space in FIFO over 32 bytes, DMA accesses
memory
[3]
[2]
[1]
[0]
EPA_STL
EPA_RDY
EPA_RST
EPA_EN
Set the Endpoint A stall
The memory is ready for Endpoint A to access
Endpoint A reset
Endpoint A enable
USB Endpoint A interrupt enable Register (EPA_IE)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EPA_IE
0xFFF06050
R/W USB endpoint A Interrupt Enable register 0x0000_0000
31
23
30
29
21
28
20
27
Reserved
19
Reserved
11
Reserved
26
18
25
17
24
16
22
14
6
15
7
13
12
10
2
9
8
5
4
3
1
0
EPA_BUS_ERR_IE
EPA_DMA_IE EPA_ALT_IE
EPA_TK_IE
EPA_STL_IE
Reserved
EPA_CF_IE
Publication Release Date: September 22, 2006
Revision A2
- 211 -
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