W90N745CD/W90N745CDG
BITS
[31:2]
DESCRIPTIONS
Reserved
USB Bus D+ Signal Status
0: USB Bus D+ Signal is low
1: USB Bus D+ Signal is high
[1]
[0]
USB_DPS
USB_DMS
USB Bus D- Signal Status
0: USB Bus D- Signal is low
1: USB Bus D- Signal is high
USB Engine Register (USB_ENG)
REGISTER
ADDRESS
R/W
DESCRIPTION
USB Engine Register
RESET VALUE
USB_ENG
0xFFF0603C
R/W
0x0000_0000
31
23
30
29
21
28
20
27
26
18
25
17
24
16
Reserved
19
22
14
6
Reserved
15
7
13
5
12
4
11
Reserved
3
10
9
1
8
0
2
Reserved
SDO_RD
CV_LDA
CV_STL
CV_DAT
BITS
DESCRIPTIONS
[31:4]
Reserved
Setup or Bulk-Out Data Read Control
0: NO Operation
1: Read Setup or Bulk-Out Data from USB Host
NOTE: this bit will auto clear after 32 HCLK
[3]
[2]
SDO_RD
CV_LDA
USB Class and Vendor Command Last Data Packet Control
0: NO Operation
1: Last Data Packet for Data Input of Class and Vendor Command
NOTE: this bit will auto clear after 32 HCLK
Publication Release Date: September 22, 2006
- 207 -
Revision A2
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