W90N745CD/W90N745CDG
MAC Receive Pause Count Register (MRPC)
The EMC of W90N745 supports the PAUSE control frame reception and recognition. If EMC received
a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored in
the MRPC register. The MRPC register will keep the same while Tx of EMC is pausing due to the
PAUSE control frame is received. The MRPC is read only and write to this register has no effect.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MRPC
0xFFF0_30BC
R
MAC Receive Pause Count Register
0x0000_0000
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
Reserved
19
Reserved
26
18
10
2
25
17
9
24
16
8
11
MRPC
MRPC
3
1
0
BITS
DESCRIPTIONS
[31:16]
Reserved
MRPC
-
The MAC Receive Pause Count keeps the operand field of the
PAUSE control frame. It indicates how many slot time (512 bit time)
the Tx of EMC will be paused.
[15:0]
MAC Receive Pause Current Count Register (MRPCC)
The EMC of W90N745 supports the PAUSE control frame reception and recognition. If EMC received
a PAUSE control frame, the operand field of the PAUSE control frame will be extracted and stored into
a down count timer. The MRPCC shows the current value of that down count timer for S/W to know
how long the Tx of EMC will be paused. The MRPCC is read only and write to this register has no
effect.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MAC Receive Pause Current Count
Register
MRPCC
0xFFF0_30C0
R
0x0000_0000
Publication Release Date: September 22, 2006
Revision A2
- 145 -
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