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W90N745CDG 参数 Datasheet PDF下载

W90N745CDG图片预览
型号: W90N745CDG
PDF下载: 下载PDF文件 查看货源
内容描述: 16位/ 32位ARM微控制器 [16/32-bit ARM microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 422 页 / 2455 K
品牌: WINBOND [ WINBOND ]
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W90N745CD/W90N745CDG  
BITS  
DESCRIPTIONS  
[31:12] Reserved  
-
The Transmission Halted high indicates the next normal packet transmission  
process will be halted because the bit TXON of MCMDR is disabled be S/W.  
1’b0: Next normal packet transmission process will go on.  
[11]  
[10]  
TXHA  
1’b1: Next normal packet transmission process will be halted.  
The Signal Quality Error high indicates the SQE error found at end of packet  
transmission on 10Mbps half-duplex mode. The SQE error check will only be  
done while both bit EnSQE of MCMDR is enabled and EMC is operating on  
10Mbps half-duplex mode.  
SQE  
1’b0: No SQE error found at end of packet transmission.  
1’b0: SQE error found at end of packet transmission.  
The Transmission Paused high indicates the next normal packet  
transmission process will be paused temporally because EMC received a  
PAUSE control frame, or S/W set bit SDPZ of MCMDR and make EMC to  
transmit a PAUSE control frame out.  
1’b0: Next normal packet transmission process will go on.  
1’b1: Next normal packet transmission process will be paused.  
[9]  
[8]  
PAU  
DEF  
The Deferred Transmission high indicates the packet transmission has  
deferred once. The DEF is only available while EMC is operating on half-  
duplex mode.  
1’b0: Packet transmission doesn’t defer.  
1’b1: Packet transmission has deferred once.  
The Collision Count indicates the how many collision occurred consecutively  
during a packet transmission. If the packet incurred 16 consecutive collisions  
during transmission, the CCNT will be 4’h0 and bit TXABT will be set to 1.  
[7:4]  
[3]  
CCNT  
Reserved  
-
The RxFIFO Full indicates the RxFIFO is full due to four 64-byte packets are  
kept in RxFIFO and the following incoming packet will be dropped.  
1’b0: The RxFIFO is not full.  
[2]  
[1]  
[0]  
RFFull  
RXHA  
CFR  
1’b1: The RxFIFO is full and the following incoming packet will be dropped.  
The Receive Halted high indicates the next normal packet reception process  
will be halted because the bit RXON of MCMDR is disabled be S/W.  
1’b0: Next normal packet reception process will go on.  
1’b1: Next normal packet reception process will be halted.  
The Control Frame Received high indicates EMC receives a flow control  
frame. The CFR only available while EMC is operating on full duplex mode.  
1’b0: The EMC doesn’t receive the flow control frame.  
1’b1: The EMC receives a flow control frame.  
Publication Release Date: September 22, 2006  
- 143 -  
Revision A2  
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