W90N745CD/W90N745CDG
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
RXDLSA
19
RXDLSA
11
RXDLSA
26
18
10
2
25
17
9
24
16
8
3
1
0
RXDLSA
BITS
DESCRIPTIONS
The RXDLSA(Receive Descriptor Link-List Start Address) keeps
the start address of receive descriptor link-list. If the S/W enables the
bit RXON of MCMDR register, the content of RXDLSA will be loaded
into the current receive descriptor start address register (CRXDSA).
The RXDLSA doesn’t be updated by EMC. During the operation,
EMC will ignore the bits [1:0] of RXDLSA. This means that each Rx
descriptor always must locate at word boundary memory address.
[31:0]
RXDLSA
MAC Command Register (MCMDR)
The MCMDR provides the control information for EMC. Some command settings affect both frame
transmission and reception, such as bit FDUP, the full/half duplex mode selection, or bit OPMOD, the
100/10M bps mode selection. Some command settings control frame transmission and reception
separately, likes bit TXON and RXON.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MCMDR
0xFFF0_3090 R/W MAC Command Register
0x0000_0000
31
30
22
14
6
29
28
Reserved
20
27
26
25
17
24
SWR
16
23
21
LBK
13
19
EnMDC
11
18
FDUP
10
Reserved
OPMOD
12
EnSQE
9
SDPZ
8
15
Reserved
NDEF
1
TXON
0
7
5
4
3
2
Reserved
SPCRC
AEP
ACP
ARP
ALP
RXON
- 116 -
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