W90N745CD/W90N745CDG
Continued.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
Status Registers (11)
Current Transmit Descriptor Start
Address Register
CTXDSA
CTXBSA
CRXDSA
CRXBSA
0xFFF0_30CC
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Current Transmit Buffer Start Address
Register
0xFFF0_30D0
0xFFF0_30D4
0xFFF0_30D8
Current Receive Descriptor Start
Address Register
Current Receive Buffer Start Address
Register
Diagnostic Registers (7)
RXFSM
TXFSM
FSM0
0xFFF0_3200
0xFFF0_3204
0xFFF0_3208
0xFFF0_320C
0xFFF0_3210
0xFFF0_3214
0xFFF0_3300
R
R
Receive Finite State Machine Register
Transmit Finite State Machine Register
Finite State Machine Register 0
Finite State Machine Register 1
Debug Configuration Register
0x0081_1101
0x0101_1101
0x0001_0101
0x1100_0100
0x0000_003F
0x0000_0000
0x0000_0000
R
FSM1
R
DCR
R/W
R
DMMIR
BISTR
Debug Mode MAC Information Register
BIST Mode Register
R/W
Publication Release Date: September 22, 2006
Revision A2
- 105 -
WINBOND [ WINBOND ]
