W90N745CD/W90N745CDG
Continued.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
CONTROL REGISTERS (44)
CAM12M
CAM12L
CAM13M
CAM13L
CAM14M
CAM14L
CAM15M
CAM15L
0xFFF0_3068
0xFFF0_306C
0xFFF0_3070
0xFFF0_3074
0xFFF0_3078
0xFFF0_307C
0xFFF0_3080
0xFFF0_3084
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CAM12 Most Significant Word Register
CAM12 Least Significant Word Register
CAM13 Most Significant Word Register
CAM13 Least Significant Word Register
CAM14 Most Significant Word Register
CAM14 Least Significant Word Register
CAM15 Most Significant Word Register
CAM15 Least Significant Word Register
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Transmit Descriptor Link List Start
Address Register
TXDLSA
RXDLSA
0xFFF0_3088
0xFFF0_308C
R/W
R/W
0xFFFF_FFFC
0xFFFF_FFFC
Receive Descriptor Link List Start
Address Register
MCMDR
MIID
0xFFF0_3090
0xFFF0_3094
R/W
R/W
MAC Command Register
0x0000_0000
0x0000_0000
MII Management Data Register
MII Management Control and Address
Register
MIIDA
0xFFF0_3098
R/W
0x0090_0000
FFTCR
TSDR
RSDR
0xFFF0_309C
0xFFF0_30A0
0xFFF0_30A4
R/W
W
FIFO Threshold Control Register
Transmit Start Demand Register
Receive Start Demand Register
0x0000_0101
Undefined
W
Undefined
Maximum Receive Frame Control
Register
DMARFC
MIEN
0xFFF0_30A8
0xFFF0_30AC
R/W
R/W
0x0000_0800
0x0000_0000
MAC Interrupt Enable Register
Status Registers (11)
MISTA
MGSTA
MPCNT
MRPC
0xFFF0_30B0
R/W
R/W
R/W
R
MAC Interrupt Status Register
MAC General Status Register
Missed Packet Count Register
MAC Receive Pause Count Register
0x0000_0000
0x0000_0000
0x0000_7FFF
0x0000_0000
0xFFF0_30B4
0xFFF0_30B8
0xFFF0_30BC
MAC Receive Pause Current Count
Register
MRPCC
0xFFF0_30C0
R
0x0000_0000
MREPC
0xFFF0_30C4
0xFFF0_30C8
R
MAC Remote Pause Count Register
DMA Receive Frame Status Register
0x0000_0000
0x0000_0000
DMARFS
R/W
- 104 -
WINBOND [ WINBOND ]
