W83697HF/F
6.3 Extended Capabilities Parallel (ECP) Port
This port is software and hardware compatible with existing parallel ports, so it may be used as a
standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that
supports DMA for ECP in both the forward (host to peripheral) and reverse (peripheral to host) directions.
Small FIFOs are used in both forward and reverse directions to improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes. The ECP port supports an automatic handshake for the
standard parallel port to improve compatibility mode transfer speed.
The ECP port supports run-length-encoded (RLE) decompression (required) in hardware. Compression is
accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times
the next byte is to be repeated. Hardware support for compression is optional.
For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA
Interface Standard.
6.3.1 ECP Register and Mode Definitions
NAME
data
ADDRESS
Base+000h
Base+000h
Base+001h
Base+002h
Base+400h
Base+400h
Base+400h
Base+400h
Base+401h
Base+402h
I/O
R/W
R/W
R
ECP MODES
000-001
011
FUNCTION
Data Register
ecpAFifo
dsr
ECP FIFO (Address)
Status Register
All
dcr
R/W
R/W
R/W
R/W
R
All
Control Register
cFifo
010
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
ecpDFifo
tFifo
011
110
cnfgA
cnfgB
ecr
111
Configuration Register A
Configuration Register B
Extended Control Register
R/W
R/W
111
All
Note: The base ad dresses are specified by CR23, which are determined by configuration register or hardware setting.
MODE
000
001
010
011
100
101
110
111
DESCRIPTION
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled in the CR9 and CR0 to select ECP/EPP mode)
Reserved
Test mode
Configuration mode
Note: The mode selection bits are bit 7 -5 of the Extended Control Register.
Publication Release Date: Feb. 2002
Revision 0.70
- 69 -
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