W83697HF/F
The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write
operation. The leading edge of IOW# causes an EPP address write cycle to be performed, and the
trailing edge of IOW# latches the data for the duration of the EPP write cycle.
PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read
cycle to be performed and the data to be output to the host CPU.
6.2.5 EPP Data Port 0-3
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
7
6
5
4
3
2
1
0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
6.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
Data Port (R/W)
7
6
5
PD5
PE
1
4
3
2
PD2
1
1
PD1
0
PD7
PD6
PD4
PD3
PD0
Status Buffer (Read)
ERROF#
BUSY# ACK#
SLCT
IRQEN
1
TMOUT
STROBE#
Control Swapper
(Read)
1
1
SLIN
INIT#
AUTOFD#
Control Latch (Write)
EPP Address Port R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
1
1
DIR
PD5
PD5
PD5
PD5
PD5
IRQ
PD4
PD4
PD4
PD4
PD4
SLIN
PD3
PD3
PD3
PD3
PD3
INIT#
PD2
PD2
PD2
PD2
PD2
AUTOFD#
PD1
STROBE#
PD0
PD7
PD7
PD7
PD7
PD7
PD6
PD6
PD6
PD6
PD6
PD1
PD0
PD1
PD0
PD1
PD0
PD1
PD0
Publication Release Date: Feb. 2002
Revision 0.70
- 67 -
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