W83627HF/ F/ HG/ G
CRE5 （Default 0x00）
BIT
DESCRIPTION
7
Reserved
6 - 0
Compared Code Length. When the compared codes are storaged in the data register,
these data length should be written to this register.
CRE6 （Default 0x00）
BIT
DESCRIPTION
7
6
Reserved
Chassis Status Clear.（availibale for A Version only）
1： Clear CASEOPEN#（Pin 76）event.
0： Disable clear function.
Set this bit to “1” will make hardware monitor register index 42, bit 4 cleared unceas-
ingly. Therefore, next Case-open Event can not be triggered again until this bit Is
cleared to “0”. This bit is available for W83627HF A Version only, please refer to Hard-
ware Monitor Register Index 46, bit 7 for other version.
5 - 0
CIR Baud Rate Divisor. The clock base of CIR is 32khz, so that the baud rate is 32khz
divided by（ CIR Baud Rate Divisor + 1）.
CRE7 （Default 0x00）
BIT
DESCRIPTION
7
6
5
4
3
Reaerved.
Reserved.
Reserved.
Reserved.
SELWDTORST. Watch Dog Timer Reset Control.
0： Indicates that Watch Dog Timer is reset by LPC_RST.
1： Indicates that Watch Dog Timer is reset by PWR_OK.
2
1
Reset CIR Power-On function. After using CIR power-on, the software should write
logical 1 to restart CIR power-on function.
Invert RX Data.
1： Inverting RX Data.
0： Not inverting RX Data.
Enable Demodulation.
0
1： Enable received signal to demodulate.
0： Disable received signal to demodulate.
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