W83195WG-382/W83195CG-382
STEPLESS FOR ATI K8 CLOCK GENERATOR
SRCCLK0 is controlled by the CLREQB# pin
1: Controllable
0: Uncontrollable
PCI0 output control
1: Enable
0: Disable
HTTCLK0 output control
1: Enable
2
1
0
CLREQB0#_Ctr
PCIEN
0
1
1
R/W
R/W
R/W
HTTEN
0: Disable
7.5 Register 4: ( Default : FEh)
AFFECTED PIN/
FUNCTION NAME(S)
BIT
PWD
FUNCTION DESCRIPTION
TYPE
7
6
5
Reserved
1
1
1
Reserved
Reserved
Reserved
R/W
R/W
R/W
Reserved
Reserved
PREF2 output control
1: Enable
0: Disable
PREF1 output control
1: Enable
0: Disable
4
3
2
REFEN<2>
REFEN<1>
REFEN<0>
1
1
1
R/W
R/W
R/W
PREF0 output control
1: Enable
0: Disable
PUSB48 output control
1: Enable
0: Disable
1
0
F48EN
1
0
R/W
R/W
Reserved
Reserved
7.6 Register 5: ( Default : 02h )
AFFECTED PIN/
FUNCTION NAME(S)
BIT
PWD
FUNCTION DESCRIPTION
TYPE
7
Reserved
0
Reserved
R/W
Program this bit =>
1 : Enable Watchdog Timer feature.
0 : Disable Watchdog Timer feature.
Enable WD sequence =>
6
CNT_EN
0
Program this bit to 1 firstly, then program the
Reg-20 to start the counting
Read-back this bit =>
R/W
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
Publication Release Date: Feb 2006
Revision 0.6
- 8 -
WINBOND [ WINBOND ]
