W78E516B
Data Read Cycle
PARAMETER
RD
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
NOTES
1, 2
DAR
T
CP
3 T
-
-
-
-
CP+
D
D
D
-
3 T
ALE Low to
Low
DDA
T
CP
CP
CP
-
4 T
nS
1
RD
Low to Data Valid
DDH
T
0
2 T
2 T
-
nS
RD
RD
Data Hold from
Data Float from
High
High
DDZ
T
0
nS
DRD
T
CP
6 T
nS
2
CP
6 T
-
RD
Pulse Width
Notes:
CP
1. Data memory access time is 8 T
.
2. " " (due to buffer driving delay and wire loading) is 20 nS.
D
Data Write Cycle
PARAMETER
WR
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
DAW
T
-
-
-
CP
CP
D
+
D
D
D
D
3 T
-
3 T
ALE Low to
Low
WR
DAD
T
-
-
-
nS
CP
1 T
1 T
6 T
-
Data Valid to
Low
WR
DWD
T
nS
CP
-
Data Hold from
High
DWR
T
CP
6 T
nS
CP
-
WR
Pulse Width
Note: " " (due to buffer driving delay and wire loading) is 20 nS.
D
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
PDS
T
1 TCP
0
-
-
-
-
-
-
PDH
T
nS
PDA
T
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 16 -
WINBOND [ WINBOND ]
