W78E365/W78E365A
8.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
T
DWD
T
DAD
T
T
DWR
DAW
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
-
nS
3 TCP-Δ
1 TCP-Δ
1 TCP-Δ
6 TCP-Δ
3 TCP+Δ
TDAD
TDWD
TDWR
-
-
-
-
-
nS
nS
nS
6 TCP
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
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