W78E365/W78E365A
8.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
T
T
DDA
DAR
T
T
DDH, DDZ
T
DRD
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
SYMBOL
TDAR
MIN.
TYP.
MAX.
3 TCP+Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
1
-
3 TCP-Δ
TDDA
-
-
nS
TDDH
0
0
-
-
nS
TDDZ
nS
TDRD
6 TCP
nS
2
6 TCP-Δ
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: January 10, 2007
Revision A9
- 31 -
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