W78E365/W78E365A
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
T
ALW
T
APL
PSEN
T
PSW
T
AAS
PORT 2
PORT 0
T
PDA
T
AAH
T
T
PDH, PDZ
A0-A7
A0-A7
Code A0-A7
Code
Data
Data
A0-A7
PARAMETER
SYMBOL
TAAS
MIN.
1 TCP-Δ
TYP.
MAX.
UNIT
nS
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
-
-
-
-
-
-
4
1, 4
4
TAAH
nS
1 TCP-Δ
TAPL
TPDA
TPDH
TPDZ
TALW
TPSW
nS
1 TCP-Δ
ALE Low to PSEN Low
-
-
-
-
2 TCP
nS
nS
nS
nS
nS
2
3
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
0
1 TCP
0
1 TCP
2 TCP
3 TCP
-
-
4
4
2 TCP-Δ
3 TCP-Δ
PSEN Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
- 30 -
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