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W25Q20BWSNIP 参数 Datasheet PDF下载

W25Q20BWSNIP图片预览
型号: W25Q20BWSNIP
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 1.8V 2M位串行闪存 [1.8V 2M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 70 页 / 2014 K
品牌: WINBOND [ WINBOND ]
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W25Q20BW  
8.2.38 Read Security Registers (48h)  
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data  
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving  
the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and  
eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK  
pin. After the address is received, the data byte of the addressed memory location will be shifted out on  
the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is  
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte  
address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register,  
and continue to increment. The instruction is completed by driving /CS high. The Read Security Register  
instruction sequence is shown in figure 36. If a Read Security Register instruction is issued while an  
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any  
effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a  
maximum of FR (see AC Electrical Characteristics).  
ADDRESS  
A23-16  
00h  
A15-12  
0 0 0 0  
0 0 0 1  
0 0 1 0  
0 0 1 1  
A11-8  
0 0 0 0  
0 0 0 0  
0 0 0 0  
0 0 0 0  
A7-0  
Security Register #0*  
Security Register #1  
Security Register #2  
Security Register #3  
Byte Address  
Byte Address  
Byte Address  
Byte Address  
00h  
00h  
00h  
* Please note that Security Register 0 is Reserved by Winbond for future use. It is  
recommended to use Security registers 1- 3 before using register 0.  
Instruction (48h)  
Figure 36. Read Security Registers Instruction Sequence  
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