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W25Q128BV 参数 Datasheet PDF下载

W25Q128BV图片预览
型号: W25Q128BV
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 3V 128M位串行闪存 [3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 74 页 / 756 K
品牌: WINBOND [ WINBOND ]
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W25Q128BV  
6. FUNCTIONAL DESCRIPTIONS  
6.1 SPI OPERATIONS  
6.1.1 Standard SPI Instructions  
The W25Q128BV is accessed through an SPI compatible bus consisting of four signals: Serial Clock  
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions  
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of  
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.  
SPI bus operation Mode 0 (0, 0) and 3 (1, 1) are supported. The primary difference between Mode 0 and  
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is  
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and  
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.  
6.1.2 Dual SPI Instructions  
The W25Q128BV supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast  
Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at  
two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for  
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical  
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become  
bidirectional I/O pins: IO0 and IO1.  
6.1.3 Quad SPI Instructions  
The W25Q128BV supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast  
Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)” instructions.  
These instructions allow data to be transferred to or from the device six to eight times the rate of ordinary  
Serial Flash. The Quad Read instructions offer a significant improvement in continuous and random  
access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP).  
When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP  
and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad  
Enable bit (QE) in Status Register-2 to be set.  
6.1.4 Hold Function  
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q128BV operation to be  
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where  
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer  
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD  
function can save the state of the instruction and the data in the buffer so programming can resume where  
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual  
SPI operation, not during Quad SPI.  
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on  
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the  
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the  
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD  
Publication Release Date: April 01, 2011  
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Revision E