BRIGHT
Microelectronics
Inc.
Preliminary BM29F400T/BM29F400B
Erase and Programming Performance
PARAMETER
MIN.
LIMITS
TYP.
0.33
2.4
MAX.
15
UNIT
sec
Sector Erase Time
Chip Erase Time
Byte Programming Time
Chip Programming Time
120
400
200
sec
16
us
8
sec
Erase/Program Cycles
10,000
100,000
cycles
Latch Up Characteristics
PARAMETER
MIN.
MAX.
Input Voltage with respect to Vss on all I/O
pins
-1.0V
Vcc + 1.0V
Vcc Current
-100 mA
+ 100 mA
Note: Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
CAPACITANCE
TSOP Pin
PARAMETER
Input Capacitance
SYMBOL
CIN
TEST SETUP
VIN = 0
TYP.
MAX.
UNIT
6
8.5
8
7.5
12
10
pF
pF
pF
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
COUT
CIN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°, f = 1.0 MHz.
SOP Pin
PARAMETER
Input Capacitance
SYMBOL
CIN
TEST SETUP
VIN = 0
TYP.
6
MAX.
7.5
12
UNIT
pF
Output Capacitance
Control Pin Capacitance
COUT
CIN2
VOUT = 0
VIN = 0
8.5
8
pF
10
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°, f = 1.0 MHz.
Data Retention
PARAMETER
TEST CONDITIONS
MIN.
10
UNIT
Minimum Pattern Data Retention Time
Minimum Pattern Data Retention Time
Years
Years
150°
125°
20
- 34 -
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