BRIGHT
Microelectronics
Inc.
Preliminary BM29F400T/BM29F400B
Byte/Word programming is allowed in any sequence, and across sector boundaries. However,
remember that a data "0" cannot be programmed to a data "1". Only erase operations can convert a
logical "0" to a logical "1". Attempting to program data from "0" to "1" may cause the device to exceed
time limits, or even worse, result in an apparent success according to the Data Polling algorithm. In
the later case, however, a subsequent read of this bit will show that the data is still a logical "0".
Figure 1 illustrates the Byte/Word Programming Algorithm using typical command strings and bus
operations.
The device will ignore any commands written to the chip during execution of the internal Byte/Word
Programming Algorithm. If a hardware RESET occurs during the Byte/Word Programming operation,
the data at that particular address location will be corrupted.
Chip Erase Command
Chip erase is a six bus cycle operation (see Table 6). The chip erase begins on the rising edge of the
last WE pulse in the command sequence.
Upon executing the Chip Erase command sequence, the device's internal state machine executes an
internal erase algorithm. The system is not required to provide further controls or timings. The device
will automatically provide adequate internally generated erase pulses and verify chip erase within the
proper cell margins. During chip erase, all sectors of the device are erased except protected sectors.
During Chip Erase, data bit DQ7 shows a logical "0". This operation is known as Data Polling. The
erase operation is completed when the data on DQ7 is a logical "1" (see Write Operation Status
section). Upon completion of the Chip Erase operation, the device returns to read mode. At this time,
the address pins are no longer latched. Note that Data Polling must be performed at a sector address
within any of the sectors being erased and not a protected sector to ensure that DQ7 returns a logical
"1" upon completion of the Chip Erase operation.
Figure 2 illustrates the Chip Erase Algorithm using typical command strings and bus operations.
The device will ignore any commands written to the chip during execution of the internal Chip Erase
algorithm. If a hardware RESET occurs during the Chip Erase operation, the data in the device will
be corrupted.
Sector Erase Command
Sector erase is a six bus cycle operation (see Table 6). The sector address (any address location
within the desired sector) is latched on the falling edge of WE , while the command data is latched on
the rising edge of WE . An internal device timer will initiate the Sector Erase operation 100 mS ±20%
(80 uS to 120 uS) from the rising edge of the WE pulse for the last Sector Erase command entered
on the device.
Upon executing the Sector Erase command sequence, the device's internal state machine executes
an internal erase algorithm. The system is not required to provide further controls or timings. The
device automatically provides adequate internally generated erase pulses and verify sector erase
within the proper cell margins. Protected sectors of the device will not be erased, even if they are
selected with the Sector Erase command.
Multiple sectors can be erased simultaneously by writing the sixth bus cycle command of the Sector
Erase command for each sector to be erased. The time between initiation of the next Sector Erase
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