Preliminary W27C4096
256K ´ 16 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27C4096 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 262144 ´ 16 bits that operates on a single 5 volt power supply. The W27C4096
provides an electrical chip erase function.
FEATURES
· High speed access time:
120/150 nS (max.)
· +14V erase/+12V programming voltage
· Fully static operation
· Read operating current: 30 mA (max.)
· Erase/Programming operating current
30 mA (max.)
· All inputs and outputs directly TTL/CMOS
compatible
· Three-state outputs
· Available packages: 40-pin 600 mil DIP, TSOP
and 44-pin PLCC
· Standby current: 100 mA (max.)
· Single 5V power supply
PIN CONFIGURATIONS
BLOCK DIAGRAM
VPP
1
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Q0
.
.
2
CE
Q15
Q14
Q13
Q12
Q11
Q10
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
3
CE
OE
OUTPUT
BUFFER
CONTROL
4
5
6
Q15
7
8
9
40-pin
DIP
Q9
Q8
GND
Q7
10
11
12
13
14
15
16
17
18
19
20
Q6
Q5
Q4
Q3
Q2
Q1
Q0
A0
A4
A3
A2
A1
.
.
CORE
ARRAY
DECODER
A0
OE
A17
/
C
E
V
p
p
Q
1
3
Q
1
4
Q
1
5
A
1
7
A
1
6
A
1
5
A
1
4
V
C
C
N
C
V
CC
6
4
2
43 42
44
5
3
1
41 40
39
38
37
36
35
34
33
A13
7
Q12
Q11
Q10
Q9
GND
8
A12
A11
A10
A9
V
9
PP
10
11
12
13
14
15
16
17
Q8
44-pin
PLCC
GND
NC
A8
GND
NC
Q7
32
31
30
A7
Q6
PIN DESCRIPTION
A6
Q5
Q4
29
A5
18 19 20 21 22 23 24 25 26 27 28
SYMBOL
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Q
3
Q
2
Q
1
N
C
A
0
A
2
A
3
Q
0
/
O
E
A
1
A
4
A0- A17
Q0- Q15
CE
40
1
2
3
GND
A8
A7
A9
39
38
37
36
35
34
A10
A11
A12
A6
4
5
A5
A4
A3
A2
A13
A14
A15
A16
6
7
Chip Enable
33
32
8
40-pin
TSOP
A1
A17
VCC
9
10
Output Enable
Program/Erase Supply Voltage
Power Supply
OE
VPP
VCC
GND
NC
A0
OE
Q0
Q1
Q2
Q3
31
30
29
28
27
26
25
VPP
11
12
13
14
15
16
17
18
19
20
CE
Q15
Q14
Q13
Q12
Q4
Q5
Q11
Q10
Q9
24
23
Q6
Q7
Q8
Ground
22
21
Q8
No Connection
Publication Release Date: March 1999
Revision A1
- 1 -
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