WCSS0418V1F
Timing Diagrams (continued)
Read/Write Cycle Timing
tCYC
tCL
tCH
CLK
tAH
tAS
A
D
B
C
ADD
tADH
tADS
ADSP
tADH
tADS
ADSC
ADV
tADVH
tADVS
tCEH
tCES
CE1
tCEH
tCES
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tEOHZ
tCLZ
Data
In/Out
Q
(B+3)
D
(C+1)
D
(C+2)
D
(C+3)
Q
(B+2)
Q
(B+1)
Q(B)
Q(B)
D(C)
Q(D)
Q(A)
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table)
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
Document #: 38-05245 Rev. **
Page 12 of 18
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