WCSS0418V1F
Timing Diagrams (continued)
Pipeline Timing
tCYC
tCL
tCH
CLK
tAS
C
E
F
G
H
B
D
A
ADD
tADH
tADS
ADSP
ADSC
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data
D (E)
D (F)
D (H)
D C)
Q(A)
D (G)
Q(B)
Q(C)
Q(D)
tCDV
tDOH
tCHZ
Device originally
deselected
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= UNDEFINED
= DON’T CARE
Document #: 38-05245 Rev. **
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