WCSN0436V1P
and DP
[3:0]
are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The WCSN0436V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address in-
puts. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS
[3:0]
inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Linear Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
10
11
00
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
00
01
10
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
Cycle Description Truth Table
[
1, 2, 3, 4, 5, 6
]
Operation
Deselected
Suspend
Begin Read
Begin Write
Burst Read
Operation
Address
Used
External
-
External
External
Internal
CE
1
X
0
0
X
CEN
0
1
0
0
0
ADV/
LD/
L
X
0
0
1
WE
X
X
1
0
X
BWS
x
X
X
X
Valid
X
CLK
L-H
L-H
L-H
L-H
L-H
Comments
I/Os three-state following next rec-
ognized clock.
Clock ignored, all operations sus-
pended.
Address latched.
Address latched, data presented
two valid clocks later.
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS
[3:0]
.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05246 Rev. **
Page 5 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
