WCSN0436V1P
Pin Definitions
Pin Number
50–44,
81–82, 99,
100, 32–37
96–93
Name
A
[16:0]
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
and DP
0
, BWS
1
controls DQ
[15:8]
and DP
1
, BWS
2
controls DQ
[23:16]
and DP
2
, BWS
3
controls
DQ
[31:24]
and DP
3
. See Write Cycle Description table for details.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
, and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence, during
the first clock when emerging from a deselected state, when the device has been
deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[16:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[31:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
[31:0]
. During write sequences, DP
0
is controlled by BWS
0
, DP
1
is controlled by
BWS
1
, DP
2
is controlled by BWS
2
, and DP
3
is controlled by BWS
3
.
Mode Input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating MODE will default HIGH, to an
interleaved burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
BWS
[3:0]
88
85
WE
ADV/LD
Input-
Synchronous
Input-
Synchronous
89
98
97
92
86
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
87
CEN
Input-
Synchronous
29–28,
DQ
[31:0]
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68, 63–62
59–56, 53–52
30, 1, 80 51
DP
[3:0]
I/O-
Synchronous
I/O-
Synchronous
Input Strap pin
31
MODE
15, 16, 41, 65,
66, 91
4, 11, 14, 20,
27, 54, 61, 70,
77
V
DD
V
DDQ
Power Supply
I/O Power
Supply
Document #: 38-05246 Rev. **
Page 3 of 14
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
