W3E32M72S-XBX
White Electronic Designs
FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
BA
1
BA
0
A
12
A
11
Address Bus
Burst
Starting Column
Address
Length
Type = Sequential Type = Interleaved
Mode Register (Mx)
14
0*
13
0*
12 11 10
9
8
7
6
5
4
3
2
1
0
A0
0
1
Operating Mode
CAS Latency BT
Burst Length
2
4
0-1
1-0
0-1
1-0
*
M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
Reserved
2
A1
0
A0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
4
0
1
8
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
1
1
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Burst Type
M3
0
1
Sequential
Interleaved
CAS Latency
M6 M5 M4
8
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Reserved
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0
selects the starting column within the block.
M11
0
M10
0
M9
0
M8
0
M7
0
M6-M0
Valid
Operating Mode
M12
0
Normal Operation
2. For a burst length of four, A2-Ai select four-data-element block; A0-1
select the starting column within the block.
0
0
0
1
0
0
Valid
Normal Operation/Reset DLL
-
-
-
All other states reserved
-
-
-
-
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputsA0-9
selects the starting column location. The value on inputA10
determines whether or notAUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; ifAUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses. Input data appearing on the DQ
is written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
